1. Field of the Invention
The present invention relates to an image display device and a driving method of the image display device, and is applicable to an active matrix type image display device using an organic EL (Electro Luminescence) element, for example. The present invention makes it possible to correct variations in characteristic of a driving transistor due to the layout of pixel circuits by correcting difference in the on characteristic of the driving transistor, which difference results from a starting position of irradiation of the driving transistor with a laser beam differing between adjacent pixel circuits created in axisymmetric form, through the setting of voltage of a driving signal for a signal line.
2. Description of the Related Art
The development of active matrix type image display devices using organic EL elements has recently been actively pursued. Image display devices using organic EL elements utilize the light emitting phenomenon of an organic thin film that emits light when an electric field is applied to the organic thin film. An organic EL element can be driven by an application voltage of 10 [V] or lower. Therefore this kind of image display device can reduce power consumption. In addition, the organic EL element is a self-luminous element. Therefore this kind of image display device does not need a backlight, and can thus be reduced in weight and thickness. Further, the organic EL element has a feature of a fast response speed of a few microseconds. Therefore this kind of image display device has a feature in that an afterimage hardly occurs at a time of displaying a moving image.
Specifically, an active matrix type image display device using the organic EL element has a display section formed by arranging pixel circuits including organic EL elements and driving circuits for driving the organic EL elements in the form of a matrix. This kind of image display device drives each pixel circuit by a signal line driving circuit and a scanning line driving circuit disposed on the periphery of the display section via a signal line and a scanning line provided in the display section, and thereby displays a desired image.
In relation to the image display device using the organic EL element, Japanese Patent Laid-Open No. 2007-310311 (referred to as Patent Document 1 hereinafter) discloses a method of forming a pixel circuit using two transistors. Thus, the method disclosed in Patent Document 1 can simplify a constitution. Patent Document 1 also discloses a constitution that corrects variations in threshold voltage and variations in mobility of a driving transistor for driving the organic EL element. Thus, the constitution disclosed in Patent Document 1 can prevent degradation in image quality due to variations in threshold voltage and variations in mobility of the driving transistor.
FIG. 6 is a block diagram showing an image display device disclosed in Patent Document 1. This image display device 1 has a display section 2 created on an insulating substrate of glass or the like. The image display device 1 has a signal line driving circuit 3 and a scanning line driving circuit 4 created on the periphery of the display section 2.
The display section 2 is formed by arranging pixel circuits 5 in the form of a matrix. Pixels (PIX) 6 are formed by organic EL elements disposed in the pixel circuits 5. Incidentally, in an image display device for color images, one pixel is formed by a plurality of sub-pixels of red, green, and blue. Thus, in the case of the image display device for color images, the display section 2 is formed by sequentially arranging pixel circuits 5 for red, green, and blue forming sub-pixels of red, green, and blue, respectively.
The signal line driving circuit 3 outputs driving signals Ssig for signal lines to signal lines DTL disposed in the display section 2. More specifically, a data scan circuit 3A in the signal line driving circuit 3 sequentially latches image data D1 input in order of raster scanning, distributes the image data D1 to the signal lines DTL, and thereafter subjects each piece of the image data D1 to digital-to-analog conversion processing. The signal line driving circuit 3 generates the driving signals Ssig by processing a result of the digital-to-analog conversion. Thereby the image display device 1 sets the gradation of each pixel circuit 5 on a so-called line-sequential basis, for example.
The scanning line driving circuit 4 outputs a writing signal WS and a driving signal DS to scanning lines WSL for the writing signal and scanning lines DSL for power supply, the scanning lines WSL and the scanning lines DSL being disposed in the display section 2. The writing signal WS is a signal for performing on-off control of a writing transistor disposed in each pixel circuit 5. The driving signal DS is a signal for controlling the drain voltage of a driving transistor disposed in each pixel circuit 5. A write scan circuit (WSCN) 4A and a drive scan circuit (DSCN) 4B in the scanning line driving circuit 4 respectively generate the writing signal WS and the driving signal DS by processing a predetermined sampling pulse SP by a clock CK.
FIG. 7 is a connection diagram showing the configuration of a pixel circuit 5 in detail. In the pixel circuit 5, the cathode of an organic EL element 8 is set at a predetermined negative side voltage. In the example of FIG. 7, the negative side voltage is set at the voltage of a ground line. In the pixel circuit 5, the anode of the organic EL element 8 is connected to the source of a driving transistor Tr2. Incidentally, the driving transistor Tr2 is an N-channel type transistor formed by a TFT, for example. In the pixel circuit 5, the drain of the driving transistor Tr2 is connected to a scanning line DSL for power supply. The scanning line DSL is supplied with the driving signal DS for power supply from the scanning line driving circuit 4. Thereby the pixel circuit 5 current-drives the organic EL element 8 using the driving transistor Tr2 of a source-follower circuit configuration.
The pixel circuit 5 has a storage capacitor Cs disposed between the gate and the source of the driving transistor Tr2. The voltage of a gate side terminal of the storage capacitor Cs is set to the voltage of a driving signal Ssig by the writing signal WS. As a result, the pixel circuit 5 current-drives the organic EL element 8 by the driving transistor Tr2 according to a gate-to-source voltage Vgs corresponding to the driving signal Ssig. Incidentally, a capacitance Cel in FIG. 7 is the stray capacitance of the organic EL element 8. Suppose in the following that the capacitance Cel is sufficiently large as compared with the storage capacitor Cs, and that the parasitic capacitance of a gate node of the driving transistor Tr2 is sufficiently small as compared with the storage capacitor Cs.
Specifically, in the pixel circuit 5, the gate of the driving transistor Tr2 is connected to a signal line DTL via a writing transistor Tr1 that performs on-off operation according to the writing signal WS. Incidentally, the writing transistor Tr1 is an N-channel type transistor formed by a TFT, for example. The signal line driving circuit 3 outputs the driving signal Ssig by switching between a gradation setting voltage Vsig and a voltage Vofs for threshold voltage correction in predetermined timing. The fixed voltage Vofs for threshold voltage correction is a fixed voltage used to correct variation in threshold voltage of the driving transistor Tr2. The gradation setting voltage Vsig is a voltage specifying the light emission luminance of the organic EL element 8, and is a voltage obtained by adding the fixed voltage Vofs for threshold voltage correction to a gradation voltage Vin. The gradation voltage Vin corresponds to the light emission luminance of the organic EL element 8. The gradation voltage Vin is generated for each signal line DTL by subjecting the image data D1 distributed to each signal line DTL to digital-to-analog conversion processing.
In the pixel circuit 5, as shown in FIGS. 8A, 8B, 8C, 8D, and 8E, the writing transistor Tr1 is set in an off state by the writing signal WS during an emission period for making the organic EL element 8 emit light (FIG. 8A). In addition, in the pixel circuit 5, the driving transistor Tr2 is supplied with a power supply voltage Vcc by the driving signal DS for power supply during the emission period (FIG. 8B). Thereby, as shown in FIG. 9, the pixel circuit 5 makes the organic EL element 8 emit light with a driving current Ids corresponding to the gate-to-source voltage Vgs (FIGS. 8D and 8E) of the driving transistor Tr2, which voltage is the voltage across the storage capacitor Cs, during the emission period.
In the pixel circuit 5, the driving signal DS for power supply is lowered to a predetermined fixed voltage Vss at time t0 at which the emission period ends (FIG. 8B). The fixed voltage Vss is a sufficiently low voltage to make the drain of the driving transistor Tr2 function as a source, and is a voltage lower than the cathode voltage of the organic EL element 8.
Thereby, in the pixel circuit 5, as shown in FIG. 10, a stored charge of the terminal on the organic EL element 8 side of the storage capacitor Cs flows out to the scanning line via the driving transistor Tr2. As a result, in the pixel circuit 5, the source voltage Vs of the driving transistor Tr2 is lowered to substantially the voltage Vss (FIG. 8E), and the organic EL element 8 stops emitting light. In addition, in the pixel circuit 5, the gate voltage Vg of the driving transistor Tr2 is lowered in such a manner as to be interlocked with the lowering of the source voltage Vs (FIG. 8D).
In the pixel circuit 5, at subsequent predetermined time t1, the writing transistor Tr1 is changed to an on state by the writing signal WS (FIG. 8A), and the gate voltage Vg of the driving transistor Tr2 is set to the fixed voltage Vofs for threshold voltage correction which voltage is set in the signal line DTL (FIGS. 8C and 8D). Thereby, in the pixel circuit 5, as shown in FIG. 11, the gate-to-source voltage Vgs of the driving transistor Tr2 is set to substantially a voltage Vofs−Vss. In the pixel circuit 5, the voltage Vofs−Vss is set larger than the threshold voltage Vth of the driving transistor Tr2 by the setting of the voltages Vofs and Vss.
Thereafter, in the pixel circuit 5, the drain voltage of the driving transistor Tr2 is raised to the power supply voltage Vcc by the driving signal DS at time t2 (FIG. 8B). Thereby, in the pixel circuit 5, as shown in FIG. 12, a charging current Ids flows from the power supply Vss into the terminal on the organic EL element 8 side of the storage capacitor Cs via the driving transistor Tr2. As a result, in the pixel circuit 5, the voltage Vs of the terminal on the organic EL element 8 side of the storage capacitor Cs rises gradually. In this case, the current Ids flowing into the organic EL element 8 via the driving transistor Tr2 in the pixel circuit 5 is used to charge the capacitance Cel of the organic EL element 8 and the storage capacitor Cs. As a result, the source voltage Vs of the driving transistor Tr2 simply rises without the organic EL element 8 emitting light.
In the pixel circuit 5, when the voltage across the storage capacitor Cs becomes the threshold voltage Vth of the driving transistor Tr2, the charging current Ids stops flowing in via the driving transistor Tr2. Thus, in this case, the rise in the source voltage Vs of the driving transistor Tr2 stops when the potential difference across the storage capacitor Cs becomes the threshold voltage Vth of the driving transistor Tr2. Thereby, the pixel circuit 5 discharges the voltage across the storage capacitor Cs via the driving transistor Tr2, and sets the voltage across the storage capacitor Cs to the threshold voltage Vth of the driving transistor Tr2.
In the pixel circuit 5, at time t3 after the passage of a sufficient time to set the voltage across the storage capacitor Cs to the threshold voltage Vth of the driving transistor Tr2, as shown in FIG. 13, the writing transistor Tr1 is changed to an off state by the writing signal WS (FIG. 8A). Next, as shown in FIG. 14, the voltage of the signal line DTL is set to a gradation setting voltage Vsig (=Vin+Vofs).
In the pixel circuit 5, the writing transistor Tr1 is set in an on state at next time t4 (FIG. 8A). Thereby, in the pixel circuit 5, as shown in FIG. 15, the gate voltage Vg of the driving transistor Tr2 is set to the gradation setting voltage Vsig, and the gate-to-source voltage Vgs of the driving transistor Tr2 is set to a voltage obtained by adding the threshold voltage Vth of the driving transistor Tr2 to the gradation voltage Vin. Thereby, the pixel circuit 5 can drive the organic EL element 8 while effectively avoiding variation in the threshold voltage Vth of the driving transistor Tr2, and thus prevent degradation in image quality due to variation in light emission luminance of the organic EL element 8.
In the pixel circuit 5, when the gate voltage Vg of the driving transistor Tr2 is set to the gradation setting voltage Vsig, the gate of the driving transistor Tr2 is connected to the signal line DTL for a certain period in a state of the drain voltage of the driving transistor Tr2 being maintained at the power supply voltage Vcc. Thereby the pixel circuit 5 also corrects variation in mobility μ of the driving transistor Tr2.
Specifically, when the gate of the driving transistor Tr2 is connected to the signal line DTL by setting the writing transistor Tr1 in an on state in a state of the voltage across the storage capacitor Cs being set at the threshold voltage Vth of the driving transistor Tr2, the gate voltage Vg of the driving transistor Tr2 gradually rises from the fixed voltage Vofs, and is set to the gradation setting voltage Vsig.
In the pixel circuit 5, a writing time constant necessary for the rising of the gate voltage Vg of the driving transistor Tr2 is set shorter than a time constant necessary for the rising of the source voltage Vs of the driving transistor Tr2.
In this case, after the writing transistor Tr1 performs an on operation, the gate voltage Vg of the driving transistor Tr2 rapidly rises to the gradation setting voltage Vsig (Vofs+Vin). At the time of the rising of the gate voltage Vg, when the capacitance Cel of the organic EL element 8 is sufficiently large as compared with the storage capacitor Cs, the source voltage Vs of the driving transistor Tr2 does not change.
However, when the gate-to-source voltage Vgs of the driving transistor Tr2 exceeds the threshold voltage Vth, the current Ids flows in from the power supply Vcc via the driving transistor Tr2, and the source voltage Vs of the driving transistor Tr2 rises gradually. As a result, in the pixel circuit 5, the voltage across the storage capacitor Cs is discharged via the driving transistor Tr2, and the rising speed of the gate-to-source voltage Vgs is decreased.
The discharge speed of the voltage across the storage capacitor Cs changes according to a capability of the driving transistor Tr2. More specifically, the higher the mobility μ of the driving transistor Tr2, the faster the discharge speed.
As a result, the pixel circuit 5 is set such that the higher the mobility μ of the driving transistor Tr2, the more the voltage across the storage capacitor Cs is decreased, whereby variation in light emission luminance due to variation in mobility is corrected. Incidentally, the decrease in the voltage across the storage capacitor Cs which decrease is involved in correcting the mobility μ is denoted by ΔV in FIG. 8, FIG. 15, and FIG. 16.
In the pixel circuit 5, the writing signal WS is lowered at time t5 after the passage of the period for correcting the mobility μ. As a result, the pixel circuit 5 starts an emission period, and makes the organic EL element 8 emit light by a driving current Ids corresponding to the voltage across the storage capacitor Cs, as shown in FIG. 16. Incidentally, when the pixel circuit 5 starts the emission period, the gate voltage Vg and the source voltage Vs of the driving transistor Tr2 rise due to a so-called bootstrap circuit. Vel in FIG. 16 is the voltage of the rise.
Thereby, the pixel circuit 5 prepares for the process of correcting the threshold voltage of the driving transistor Tr2 during a period from time t0 to time t2 during which period the gate voltage of the driving transistor Tr2 is lowered to the voltage Vss. During the next period from time t2 to time t3, the voltage across the storage capacitor Cs is set to the threshold voltage Vth of the driving transistor Tr2, and thereby the threshold voltage of the driving transistor Tr2 is corrected. In addition, during a period from time t4 to time t5, the mobility μ of the driving transistor Tr2 is corrected, and the gradation setting voltage Vsig is sampled.
FIG. 17 is a plan view of the layout of a pixel circuit 5 according to the constitution disclosed in Patent Document 1. FIG. 17 is a plan view of a substrate side as viewed with members of an upper layer from the anode electrode of the organic EL element 8 removed, and is a diagram showing the layout of the driving transistor Tr2 and the like by a wiring pattern formed on the substrate. In FIG. 17, the wiring pattern of each layer is shown by different hatching. In addition, a circular mark represents an interlayer contact.
In the pixel circuit 5, first wiring is created by depositing a wiring pattern material layer on an insulating substrate 9 of glass, for example, and thereafter subjecting the wiring pattern material layer to an etching process. In the pixel circuit 5, the gate side electrode of the storage capacitor Cs, a part of the signal line DTL, and the gate electrodes G of the writing transistor Tr1 and the driving transistor Tr2 are created by the first wiring. In the pixel circuit 5, a gate insulating layer, an amorphous silicon layer and the like are next created sequentially, and thereafter the amorphous silicon layer is subjected to an annealing process by irradiation with a laser beam.
In the pixel circuit 5, second wiring is created next by depositing a wiring pattern material layer and thereafter subjecting the wiring pattern material layer to an etching process. In the pixel circuit 5, the source side electrode of the storage capacitor Cs, the source electrode S and drain electrode D of the writing transistor Tr1, and the source electrode S and drain electrode D of the driving transistor Tr2 are created by the second wiring.
Japanese Patent Laid-Open No. 2007-133284 (referred to as Patent Document 2 hereinafter) proposes a constitution in which the process of correcting variation in threshold voltage of the driving transistor Tr2 is divided and performed a plurality of times. According to the constitution disclosed in Patent Document 2, a sufficient time can be allocated to the correction of variation in threshold voltage even when a time assigned to the setting of a gradation of a pixel circuit is shortened with increase in precision. Thus, degradation in image quality due to threshold voltage variation can be prevented even when precision is increased.